1M. Sc. [Engg.] Student, Department of Electronics and Electrical Engineering, M. S. Ramaiah School of Advanced Studies, Bangalore-560 058
2Assistant Professor, Department of Electronics and Electrical Engineering, M. S. Ramaiah School of Advanced Studies, Bangalore-560 058
3Staff Manager, VLSI System Design Centre, QUALCOMM, Bangalore
Increased system complexity has led to the substitution of the traditional bottom-up design flow by systematic hierarchical design flow. With decreasing channel lengths, few key problems such as timing closure, design sign-off, routing complexity, and power dissipation arise in the design flows. Specifically, minimizing power dissipation is critical in several high-end processors.
This research aims at optimizing the design flow for power using the unified power format (UPF). The low power reduction techniques enforced in this research are multivoltage, multi-threshold voltage (Vth), and power gating with state retention. A top-down digital design flow for a flash based mixed signal microcontroller has been implemented with and without UPF synthesis flow for 45nm technology. The UPF synthesis is implemented with two voltages, 1.2V and 0.9V (Multi-VDD). Area, power and timing metrics are analyzed for the flows developed.
Power savings of about 20% are achieved in the design flow with ‘multi-threshold ’power technique compared to that of the design flow with no low power techniques employed. Similarly, 31% power savings are achieved in the design flow with the UPF implemented when compared to that of the design flow with ‘multi-threshold ’power technique employed. Thus, a cumulative power savings of 51% has been achieved in a complete power efficient design flow (UPF) compared to that of the generic top-down standard flow with no power saving techniques employed.
Low Power Format, Cell Library, Unified Power Format, signal microcontroller
