Design and Development of Cost Effective Virtex-5 General Purpose Board

This study is aims towards development of cost effective Virtex-5 board which allows designers to experiment with features of Virtex-5 LX FPGAs at affordable cost. It has many advanced interfaces like Ethernet, System Ace, Platform flash Video Codec, optional user clock, Keyboard and Mouse interface etc., These interfaces are very much useful for industrial and consumer applications. But this makes the cost of the kit very expensive for students and amateur designers. Fundamental interfaces with which the experiments and most of the operations can be carried out would be very much sufficient for them.

Power plane split is carefully made considering potential EMI issues. DDR2 signals have been grouped together according to data, mask and strobe bits. These have been routed in group in layout as well. Signal Integrity and EMI analysis have been carried out to ensure good signal quality. For DDR2 signals over shoot and undershoot in voltage levels have been diagnosed and rectified. DDR2 signals have been length matched for precision of 25mil to attain good timing of the signals. Components have been selected based on RoHS compliance abiding to EU ROHS 2002/95/EC, Obsolescence, Lead-time, risk factors like Technology, Whisker and packaging. Layer stack-up for 12 layers have been built thereby providing excellent ground reference for all signals.

Overall cost of the newly designed cost effective Virtex-5 board design is reduced to nearly 50%. Peak emission remains at 37.7 dBuV/m. As a result of Signal Integrity analysis, 14 address lines, 16 Control signals, 64 data signals, 8 data mask signals and 16 strobe signals (8 pairs) which belong to DDR2 do not have issues due to reflection.