SASTech - Technical Journal of RUAS
  • Year: 2012
  • Volume: 11
  • Issue: 2

Design and Development of Stream Processor and Texture Filtering Unit for Graphics Processor Architecture IP

  • Author:
  • Krishna Bhushan Vutukuru1, Sanket Dessai2
  • Total Page Count: 7
  • Page Number: 60 to 66

1 M. Sc. [Engg.] Student, Computer Engineering Dept.,M. S. Ramaiah School of Advanced Studies, Bangalore, 560 058

2Assistant Professor, Computer Engineering Dept.,M. S. Ramaiah School of Advanced Studies, Bangalore, 560 058

Online published on 18 February, 2020.

Abstract

Graphical Processing Units (GPUs) have become an integral part of today's mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware.

This paper presents the architectural design, modelling and simulation of reconfigurable stream processor and texture filtering unit of a GPU. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed architecture provides a high degree of scalability and flexibility to allow customization for unique applications. The designed stream processor and texture filtering unit are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.

The simulated execution time of 8-bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz. Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU.

Keywords

GPU, FPGA, Stream Processor, Texture Filtering Unit, Geometrical modelling