SASTech - Technical Journal of RUAS
  • Year: 2013
  • Volume: 12
  • Issue: 1

Design and development of camera interface controller with video pre-processing modules on fpga for mavs

  • Author:
  • O. Ranganathan1,, Abdul Imran Rasheed2
  • Total Page Count: 6
  • Page Number: 9 to 14

1 M. Sc [Engg.] student, Department of Electronics and Electrical Engineering, M. S. Ramaiah School of Advanced Studies, Bangalore-58

2Assistant Professor, Department of Electronics and Electrical Engineering, M. S. Ramaiah School of Advanced Studies, Bangalore-58

*imran@msrsas.org

Online published on 18 February, 2020.

Abstract

Over the past few years the idea of micro sized aerial vehicles shortly known as Micro Air Vehicles (MAVs) has gained mounting interest. These MAVs while flying acquire terrain images through their on board cameras and transmit the images for interpretation to base station. The onboard cameras acquire images and these images are processed and results are used for locating the next position and also the velocity with which the MAV should reach to its next position. The flying direction and speed of the MAV depends on the speed with which the images are acquired and processed. The time taken to acquire image is limited by camera frame speed, the processor speed and capability, which is observed to be greater than 30 ms from the literature. Hence the acquisition of real-time images in MAVs plays a major role in its overall functionality and performance which necessitates the dedicated camera interface module with high processing speed.

The current paper deals with the design of a new camera interface controller that has high processing speed. The first focus of the design is on developing the input interface controller module for interfacing CMOS sensor with FPGA module for converting the raw data into RGB pixel information and the output interface controller. The second focus is to synchronize all the modules of the design for proper streaming of video. A 5 MP CMOS sensor having a resolution of 2592 column by 1944 row with the frame rate of 15 fps is chosen. The captured information from the sensor is then converted into RGB pattern and processed for streaming in VGA display.

The controller is synthesized using Altera Quartus II v 12.0 and implemented on Cyclone IV E FPGA board from Altera. The synthesis of the design reports, the total number of logic elements utilized by the design as 1739 with 1062 logic registers, total number of pins configured with I/Os of the design as 455 with 44752 memory bits and one PLL circuitry utilization. The power analysis reports the total power dissipation of the design as 328.29 mW. The total acquisition time of the image from the sensor to the display is 28 ms which is less than 30 ms that makes this controller suitable for MAV applications. Further low power ASIC synthesis and implementation of the controller can be opted as a consideration for high power consumption and payload implications on MAVs

Keywords

CMOS sensor interface, Camera interface controller, MAV, Camera interface with FPGA