Design and Simulation Analysis of a Time Predictable Computer Architecture

General purpose processors are driven by the idea of optimizing for average case execution time analysis. But the processors used in real-time embedded applications must undergo timing analysis to ensure the timing constraints are met or not. Hence the Worst-Case Execution Time (WCET) analysis is important for real time applications. A Time Predictable Computer Architecture helps in simplifying the WCET analysis. In this Paper, a Time Predictable Computer Architecture is developed. This architecture is characterised by a four stage pipeline, in order execution, basic RISC instruction set, timing instructions and scratchpad memory. The four stage pipeline is selected as a trade-off between real time performance and time predictability. It is designed to detect and handle hazards by setting and resetting register when the registers are accessed to write or read. An on-chip scratchpad memory is used as an alternative to cache memory. All the instruction are loaded from the instruction memory to scratchpad memory before execution. The instructions are only executed in-order, and timing instructions are implemented to specify and ensure deadline constraints. These features make the developed architecture time predictable in nature. The developed architecture is simulated and analysed using the HASE (Hierarchical Architecture Simulation Environment) simulator. A layout of the architecture is developed to visualise the instruction flow. Simulation results show that the developed computer architecture remains time predictable when tested with varying sets of simple instructions. It would be interesting to incorporate features such as cache, branch prediction and out-of order execution into the developed architecture and analyse its effect on time predictability.