Multiplications and additions are most widely used arithmetic computations performed in all digital signal processing applications. Addition is the basic operation for many digital applications. The aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system is mainly influenced by the performance of the adders. Multipliers are also very important component in digital systems.
This paper deals with the implementation of the VLSI design of the unsigned integer shift and add multiplier using modified carry select adder technique. The ordinary carry look ahead adder based multiplier needs the delay time of 100 ns for the multiplication. In CSLA the area is reduced to 31% than in the CLAA based multiplier. The Conventional CSLA based multiplier uses the delay time of 100 ns for performing multiplication operation where as in modified CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area and power needed for CSLA multiplier is reduced by the modified CSLA based multiplier to complete the multiplication operation.
The proposed 32-bit modified CSLA design consumes 16159.38 nW power and 298 μm2 area. The proposed 64-bit modified CSLA design consumes 33417.16 nW power and 692 μm2 area. The proposed 16-bit Multiplier using modified CSLA design consumes 18093.64 nW power and 993 μm2 area. The proposed 32-bit Multiplier using modified CSLA design consumes 22793.293 nW power and 1868 μm2 area. After implementing 16-bit proposed Multiplier design, the area occupied is 298 LUT's which is reduced by 16.27% than 16-bit existing Multiplier which occupied 692 LUT's and power is reduced to 18093.64 nW. After implementing 32-bit proposed Multiplier design, the area occupied is 493 LUT's which is reduced by 14.49% than 32-bit existing Multiplier which occupied 986 LUT's and power is reduced to 22793.293 nW.
Area, Power, CSLA, Adder, Multiplier
