A Novel 8T SRAM Cell using 16 nm FinFET Technology

Stability is an important performance metric of Static Random Access Memories(SRAMs). A well-designed SRAM must have high stability. This paper proposes a novel 8 transistor SRAM cell to improve read stability and write ability. The proposed novel 8T SRAM memory cell achieves a Read Static Noise Margin (RSNM) of 517.73 mV and Write Static Noise Margin (WSNM) of 504.31 mV using 16 nm FinFET technology at 0.85 V. It provides 6.91x and 0.97x improvement in RSNM; 1.3x and 0.89x improvement in WSNM over conventional 6T and 8T SRAM cells respectively. Read and write delay per read and write operation are 0.708 ns and 0.439 ns respectively. The measured power consumption of read and write operations is 7.9988 μW and 10.020 μW respectively. The proposed 8T SRAM cell achieves better read stability and write ability while maintaining less cell delay and low power.