Design and Development of USB Based Hardware Accelerator for Embedded Systems

This paper focuses on the design and development of a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low and cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board is discussed. Execution engine of the accelerator is mapped on a FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to execute such an algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion. System can have any high level language driver and host software to off load the data to the FPGA and trigger the process using the shared memory hand shaking mechanism. Using the same shared memory FPGA can inform the host process about the completion of execution.