BCD Approach Based High Performance Floating Point Multiplier for DSP Applications

For Applications such as Digital Signal Processing (DSP), floating point computations provide higher accuracy and improved precision. IEEE-754 standard is widely used to attain the precision, but with a trade-off of accuracy due to truncation error. For an efficient hardware implementation, complexity of the architecture is the most important element. This paper proposes a combined approach of Binary Coded Decimal(BCD) and binary compuation for floating point multiplications. The developed architecture is based on formulated conditions, which speeds up the operations as well as reduces the power requirement. The developed architecture has been implemented on FPGA Virtex-6 and verified. The proposed architecture has utilized Braun's multiplier with Kogge Stone adder for performing binary multiplication. The proposed architecture utilizes 4689 slice registers, operating at speed of 40.175 MHz for 64-bit. Proposed architecture has been compared with existing design achieving 54.6% and 11.2% better delay and resource utilization respectively.