FPGA Implementation of Efficient Convolution Architecture for CNN

Face recognition, self-driving cars, object tracking and navigation applications are making a difference in society at large. The efficiency and accuracy of systems and algorithms in the applications are dependent on the amount of data utilized to perform the tasks. Over the past decades, continuous increase in the volumes of data has created the necessity of building self-learning systems. As the amount of data increases, the computation time and power requirement of architecture increases. Convolution Neural Network (CNN) is one of the deep learning algorithms that has been successfully applied in image processing applications. There is a trade off with the power and computation time as the same convolution block is utilized number of times in CNN to improve accuracy. The speed and power of CNN architecture depends significantly on the performance of the convolution block. In this paper, a power efficient convolution architecture has been proposed. In the proposed architecture, column operations have been performed simultaneously and the row operations have been carried out sequentially. The Multiplier Accumulate (MAC) unit of the proposed architecture has a conditional check block to avoid computation based on the input values. The developed convolution architecture utilizes 270 slice registers and power consumption of 3.7 mW with maximum operating frequency of 64 MHz. It has been shown that the developed architecture consumes one-fourth of the power compared to the existing architecture. The results suggest the utility of the proposed architecture as a part of applications where CNNs are used.