Design and fpga implementation of reconfigurable digital front end module of MIMO-OFDM for UWB system

The Multi Input Multi Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) based Ultra-Wideband (UWB) systems are set to revolutionize consumer electronics, in the near future. With low power consumption, high data rates up to 480 Mbps, large spatial capacity and low interference with other wireless services due to low power spectral density, MIMO-OFDM based UWB systems are the most sought after for wireless communications. The application targeted by this design was the band 1 of ‘Band group 1’ based UWB system with a center frequency of 3.432 GHz and a bandwidth of 528 MHz.

This paper focuses on FPGA implementation of Reconfigurable Digital Frontend module of MIMO-OFDM. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. Unlike the conventional OFDM based systems, Numerically Controlled Oscillators (NCO) are used for mapping modulated data onto the subcarriers. The use of NCO in the MIMO-OFDM system reduces the resource utilization of the design on FPGA along with reduced power consumption. The major modules that were designed, which constitute the digital frontend module, are Quadrature Phase Shift Keying (QPSK) modulator/demodulator, 16-Quadrature Amplitude Modulation (QAM) modulator/demodulator and NCOs. Each of the modules was tested for its functionality by developing corresponding testbenches.

This paper has resulted in a hardware implementation of the MIMO-OFDM based UWB system on a SPARTAN 3 FPGA board. The NCO based architecture utilizes 30% of slices, 27% of 4-nput LUTs, 20% of IOBs and 9% of slice Flip Flops on the SPARTAN 3 board. The NCO based architecture utilizes 70% lesser resources on the SPARTAN 3 board, than Inverse Fast Fourier Transformation (IFFT) based design. The system consumes a power of 278.48 μWatt and operates at a maximum frequency of 181.8 MHz.