Saving cache memory using a locking cache in realtime systems

Locking cache is a practical alternative to traditional caches in realtime systems. With similar performance than conventional caches, a locking cache allows a simple, accurate schedulability analysis. This work presents a new application of the locking cache. Along the modern trend to design SystemsOnaChip (SOCs) in which a single IC, usually a programmable device like an FPGA, is designed with one or more microprocessors and peripherals, a locking cache is used to reduce the cache size to the minimum that satisfies the system schedulability. Although results are not as good as the authors expected, the developed technique is promising, and future work may lead to very interesting cost reductions in the size of the memory hierarchy of realtime systems while maintaining their schedulability properties.